[ComponentDefinitionProps]
ALT_SYMBOLS=YES
CLASS=YES
PART_NUMBER=YES
TOL=YES
VALUE=YES
POWER_GROUP=YES
SWAP_INFO=YES

[ComponentInstanceProps]
GROUP=YES
ROOM=YES
VOLTAGE=YES
FSP_LIB_PART_MODEL=YES
FSP_IS_FPGA=YES
FSP_INSTANCE_NAME=YES
FSP_INSTANCE_ID=YES

[netprops]
ASSIGN_TOPOLOGY=YES
BUS_NAME=YES
CLOCK_NET=YES
DIFFERENTIAL_PAIR=YES
DIFFP_2ND_LENGTH=YES
DIFFP_LENGTH_TOL=YES
ECL=YES
ECL_TEMP=YES
ELECTRICAL_CONSTRAINT_SET=YES
EMC_CRITICAL_NET=YES
IMPEDANCE_RULE=YES
MATCHED_DELAY=YES
MAX_EXPOSED_LENGTH=YES
MAX_FINAL_SETTLE=YES
MAX_OVERSHOOT=YES
MAX_VIA_COUNT=YES
MIN_BOND_LENGTH=YES
MIN_HOLD=YES
MIN_LINE_WIDTH=YES
MIN_NECK_WIDTH=YES
MIN_NOISE_MARGIN=YES
MIN_SETUP=YES
NET_PHYSICAL_TYPE=YES
NET_SPACING_TYPE=YES
NO_GLOSS=YES
NO_PIN_ESCAPE=YES
NO_RAT=YES
NO_RIPUP=YES
NO_ROUTE=YES
NO_TEST=YES
PROBE_NUMBER=YES
PROPAGATION_DELAY=YES
RELATIVE_PROPAGATION_DELAY=YES
RATSNEST_SCHEDULE=YES
ROUTE_PRIORITY=YES
SHIELD_NET=YES
SHIELD_TYPE=YES
STUB_LENGTH=YES
SUBNET_NAME=YES
TS_ALLOWED=YES
VOLTAGE=YES
VOLTAGE_LAYER=YES
FSP_NET=YES
FSP_BUS_INDEX=YES

[functionprops]
GROUP=YES
HARD_LOCATION=YES
NO_SWAP_GATE=YES
NO_SWAP_GATE_EXT=YES
NO_SWAP_PIN=YES
ROOM=YES

[pinprops]
NO_DRC=YES
NO_PIN_ESCAPE=YES
NO_SHAPE_CONNECT=YES
NO_SWAP_PIN=YES
PIN_ESCAPE=YES