[FLASH_LIST]
//	Hardware specification version: 1226A
//
//	Flash list definition
//	Offset		abbreviation		value
//=================================================================================================================================================================================================
//						1st flash ID ( Manufacture ID )
//						2nd flash ID ( Device ID )
//						3rd flash ID
//						4th flash ID
//						LA: 5th flash ID
//	0x00		FSH_CTRL5		Flash Control5 Register ( 0x3923 )
//	0x01		FSH_CTRL6		Flash Control6 Register ( 0x3924 )
//	0x02		PARTI_SHIFT 		For formula Parti Shift Register ( 0x3914 ) in normal mode
//	0x03		BLK_SHIFT		For formula Block Shift Register ( 0x3015 ) in normal mode
//	0x04		PAGE_SHIFT		For formula Page Shift Register ( 0x3017 ) in normal mode
//	0x05		ADDR_CYCLE		Address Cycle Register ( 0x3018 )
//	0x06, 0x07	DEFECT_BLK		The percentage of defective blocks per chip
//	0x08		CE_CTRL			CE Control Register ( 0x3905 )
//	0x09		FSH_CFG			Flash Cfg Register ( 0x3919 )
//	0x0A		FSH_WR_CTRL		Flash Write Control Register ( 0x391A )
//	0x0B		FSH_RD_CTRL		Flash Read Control Register ( 0x391B )
//	0x0C		FSH_RD_CTRL2		Flash Read Control 2 Register ( 0x391C )
//	0x0D		FSH_ALE_CLE_CTRL	Flash ALE/CLE Control Register ( 0x391D )
//	0x0E		FSH_CTRL0		Flash Control0 Register ( 0x391E )
//	0x0F		FSH_CTRL1		Flash Control1 Register ( 0x391F )
//	0x10		FSH_CTRL2		Flash Control2 Register ( 0x3920 )
//	0x11		FSH_CTRL3		Flash Control3 Register ( 0x3921 )
//	0x12		CE Num			CE Num (0->1 CE, 1->2 CE, 2->4 CE)
//	0x13		MP_FACTOR		MP Factor Register ( 0x3911 )
//	0x14		BANK_SHIFT		Bank Shift Register ( 0x3916)
//	0x15		DIE_FACTOR		Die Factor Register ( 0x3912 )
//	0x16		CHIP_FACTOR		Chip Factor Register ( 0x3913 )
//	0x17		FSH_CTRL4		Flash Control4 Register ( 0x3922 )
//	0x18		FSH_CTRL7		Flash Control7 Register ( 0x3925 )
//	0x19		FSH_CTRL8		Flash Control8 Register ( 0x3926 )
//	0x1A		FSH_DQS_CTRL		Flash DQS Control Register ( 0x3928 )
//	0x1B		Parameter1 		See the Summary below:
//						bit[0]: enable read error retirement
//						bit[1]: enable program error retirement
//						bit[2]: enable erase error retirement
//						bit[3]: Reset First before flash command
//						bit[4]: read reclaim
//						bit[5]: page shift
//						bit[6]: program count
//						bit[7]: Pre-Erase (0 -> Disable, 1 -> Enable)
//	0x1C, 0x1D	Parameter2		Number of phsical page program time = (3 second/physical page program time. Hex value)
//	0x1E		Parameter3		See the Summary below:
//						bit[0]: gfFlashSLC
//						bit[1]: gfXSBMode
//						bit[2]: gfFlashIM
//						bit[3]: gfEnableI2NoWait.  When set, Parameter1.bit3 must be cleared
//						bit[4]: Synchronous mode						
//						bit[5]: enable command 10
//						bit[6]: enable password silo						
//						bit[7]: enable UART
//	0x1F		Parameter4		See the Summary below:
//						bit[1:0]: window size, (128 * (n + 1))
//						bit[3:2]: scan defect type
//						bit[5:4]: dies per CE
//						bit[6]: 2 block consist with defect
//						bit[7]: erase good block

// Hynix 26nm 32Gb MLC SDR SDP Flash 20ns 8192+640
//	                	             0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    10   11   12   13   14   15   16   17   18   19   1A   1B   1C   1D   1E   1F   		OSC	tWC	 tRC	VCC	Spec		
// H27UBG8T2BTR_R	  0xAD 0xD7 0x94 0xDA 0x74 0x14 0x22 0x04 0x0B 0x08 0x12 0x00 0x18 0x00 0x81 0x51 0xB1 0x03 0x53 0x10 0x2F 0x01 0x04 0x00 0x01 0x08 0x00 0x00 0x20 0x40 0x0A 0x07 0xD1 0x09 0x18 0x0A 0x43      		   //    20ns 	 20ns enable reclaim
H27UBG8T2BTR  	  0xAD 0xD7 0x94 0xDA 0x74 0x14 0x22 0x04 0x0B 0x08 0x12 0x00 0x18 0x00 0x81 0x32 0xB2 0x03 0x53 0x10 0x2F 0x01 0x04 0x00 0x00 0x08 0x00 0x00 0x20 0x40 0x0A 0x07 0x81 0x09 0x18 0x03 0x43      		   

[SD_CID]
// For SLC MODE
//	0x00		SAMSUNG_NORMAL_MODE
//	0x01		SAMSUNG_RELIABLE_MODE
//	0x02		IM_SLC_FA
//	0x03		IM_SLC_P1
//	0x04		IM_SLC_P2
//	0x05		IM_SLC_P3
//	0x06		IM_SLC_P4
//	0x07		SLC_Page_Shift
//	0x08		Reserved
//	0x09		Reserved
//	0x0A		Reserved
//	0x0B		Reserved
//	0x0C		Reserved
//	0x0D		Reserved
//	0x0E		Reserved
//	0x0F		Reserved

//0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F   
  0xDF 0xDA 0x00 0x00 0x00 0x00 0x00 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

[MMC_CID]
//	0x00		set feature command, enable ONFI
//	0x01		gubONFIDDR_FA
//	0x02		gubONFIDDR_P1
//	0x03		gubONFISDR_P1
//	0x04		feature address for flash output drive strength
//	0x05		drive strength setting
//	0x06		drive strength setting  I2
//	0x07		Reserved
//	0x08		Reserved
//	0x09		Reserved
//	0x0A		Reserved
//	0x0B		Reserved
//	0x0C		Reserved
//	0x0D		Reserved
//	0x0E		Reserved
//	0x0F		Reserved

//0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F   
  0xEF 0x01 0x12 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

[SD_CSD]
// 2GB
// (A) SD 2.0/SD 1.xx, 2F: Large/AG-AND/Small/Multi-Plane
// 00 3F 01 32 5F 5A 80 00 36 D8 5F FF 9E 40 00 75

// (B) SD 1.01, 2F:Large/AG-AND/Small/Multi-Plane
// 00 3F 01 32 1F 5A 80 00 36 D8 5F FF 9E 40 00 75

// Under 2GB
// (C) SD 2.0/SD 1.xx, 2F: Large/AG-AND/Small/Multi-Plane
00 3F 01 32 5F 59 80 00 36 D8 5F FF 9E 40 00 75

// (D) SD 1.01, 2F:Large/AG-AND/Small/Multi-Plane
// 00 3F 01 32 1F 59 80 00 36 D8 5F FF 9E 40 00 75

[MMC_CSD]
// 2GB
// (A) MMC 4.0, 2F: Large/Small/Multi-Plane
// 90 3F 01 2A 0F 5A 80 00 36 D8 7F E3 9E 40 00 75

// (B) MMC 3.x, 2F: Large/Small/Multi-Plane
// 8C 3F 01 2A 0F 5A 80 00 36 D8 7F E3 9E 40 00 75

// (C) MMC 4.0, 3F: AG-AND
// 90 3F 01 2A 0F 5A 80 00 36 D8 7F E3 9E 40 00 75

// (D) MMC 3.x, 3F: AG-AND
// 8C 3F 01 2A 0F 5A 80 00 36 D8 7F E3 9E 40 00 75

// Under 2GB
// (A) MMC 4.0, 2F: Large/Small/Multi-Plane
90 3F 01 2A 0F 59 80 00 36 D8 7F E3 9E 40 00 75

// (B) MMC 3.x, 2F: Large/Small/Multi-Plane
// 8C 3F 01 2A 0F 59 80 00 36 D8 7F E3 9E 40 00 75

// (C) MMC 4.0, 3F: AG-AND
// 90 3F 01 2A 0F 59 80 00 36 D8 7F E3 9E 40 00 75

// (D) MMC 3.x, 3F: AG-AND
// 8C 3F 01 2A 0F 59 80 00 36 D8 7F E3 9E 40 00 75

[SD_COMP_PARAS]
//	0x00	RDMR_CTRL0 		0x3937
//	0x01				0x39xx
//	0x02				0x39xx
//	0x03	RDMR_CTRL3		0x393A
//	0x04	RDMR_CTRL4		0x393B
//	0x05	RDMR_CTRL5		0x393C
//	0x06	RDMR_CTRL6		0x393D
//	0x07	RDMR_CTRL7		0x393E
//	0x08	RDMR_CTRL8		0x393F
//	0x09	RDMR_CTRL9		0x3940
//	0x0A	RDMR_CTRL10		0x3941
//	0x0B	RDMR_CTRL11		0x3942
//	0x0C	RDMR_CTRL12		0x3943
//	0x0D	HEADER_CTRL		0x3945		MLC = 0x01, TLC = 0x16, header type 2 cannot work correctly under 2-plane cache read with skycode 0x71
//	0x0E	TLC_CTRL 		0x3F00
//	0x0F	TLC_RDMR_BALAN		0x3F01
//	0x10	TLC_Seed_H		0x3F02
//	0x11	TLC_Seed_L		0x3F03
//	0x12	FE_RDMR_CTRL		0x3F04 
//	0x13	DQS delay fine tune	0x39E5
//	0x14	DQS read delay		0x39E6
//	0x15	FlashControl7_2		0x3925
//	0x16	UART_CTRL0		0x3E10
//	0x17	UART_CTRL1		0x3F11
//	0x18	UART_CLK_CTRL		0x3E12
//	0x19	EXT_CLK_CTRL		0x3E13
//	0x1A	ETU_CYCLE_H		0x3E14
//	0x1B	ETU_CYCLE_L		0x3E15
//	0x1C	EXT_ETU_CNT		0x3E16
//	0x1D	FlashConfigure_2	0x3919, for internal interleave only
//	0x1E	extra flags
//		bit[0]: 0 to disable checking LED pin status during initial stage, 1 to enable
//		bit[1]: 1 to enable FW solution for FE hang on
//		bit[2]: 1 to enable 2nd FlashConfigure value ,FlashConfigure_2, after reading P block for internal interleave only
//		bit[3]: 1 to enable gfSPOREnable
//	0x1F	Watch Dog	

//0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F  
  09 00 00 01 00 00 00 00 00 05 02 00 FD 01 00 00 00 00 0F 00 88 40 1C 00 00 00 00 51 00 81 09 00

[MMC_COMP_PARAS]
//	0x00	FSH_DEFECT3			0x392B
//	0x01	FSH_DEFECT2			0x392C
//	0x02	FSH_DEFECT1			0x392D
//	0x03	FSH_DEFECT0			0x392E
//	0x04	
//	0x05	USB_PARAM5(FDIO drive)		0x3D25
//	0x06	USB_PARAM6(STOP mode func sel)	0x3D26
//	0x07	USB_PARAM7(STOP mode enable)	0x3D27
//	0x08	USB_PARAM8(FE DMA control)	0x3D28
//	0x09	USB_PARAM9(OSC)			0x3D2E
//	0x0A	DRIVER_CTRL0(FOE/FWE)		0x3D2F
//	0x0B	PAD_CTRL(DQS/RB Pull Up)	0x3D33
//	0x0C	BU_SIZE_SEL			0x3D4F
//	0x0D	WAI RUSH THRESHOLD
//	0x0E	Wear Leveling (Erase count)	
//	0x0F	Wear Leveling (Read count)	
//	0x10	IM Drive strength value	
//	0x11	R-Block number	
//	0x12	C-Block number	
//	0x13	CKCON auto mode	
//	0x14	CKCON manul mode	
//	0x15	USB_PARAM9(OSC)	2		0x3D2E
//	0x16	guwScrMaxPage_H	
//	0x17	guwScrMaxPage_L
//	0x18	gubFlashType
//		[3:0] flash type
//		0: N/A
//		1: SLC
//		2: MLC
//		3: TLC
//		[7:4] flash maker
//		0: N/A
//		1: Samsung
//		2: IM
//		3: Toshiba
//		4: Hynix
//		5: Skymedi
//	0x19	
//	0x1A	Page Num_H	
//	0x1B	Page Num_L	
//	0x1C	Block_Num1_H			0x3931
//	0x1D	Block Num1_L			0x3932
//	0x1E	Block Num2_H			0x3935
//	0x1F	Block Num2_L			0x3936

//0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F  
  00 00 00 00 00 2A 48 00 0F 01 22 55 24 20 20 00 00 07 04 02 07 30 00 20 43 00 01 00 08 00 08 00

[VERSION]
04 09

[SD_EXT_CSD]
//	0x00 PHY Genesys [0x3D80] clock enable 0
//	0x01 PHY Genesys [0x3D81] clock enable 1	
//	0x02 PHY Genesys [0x3D82] clock control 0
//	0x03 PHY Genesys [0x3D83] clock control 1	
//	0x04 PHY Genesys [0x3D84] electric control 0	
//	0x05 PHY Genesys [0x3D85] electric control 1
//	0x06 PHY Genesys [0x3D86] SM bus control
//	0x07 PHY Genesys [0x3D87] resvered
//	0x08 PHY Genesys [0x3D88] function power control
//	0x09 PHY Genesys [0x3D89] function power data
//	0x0A PHY Genesys [0x3D8A] test control
//	0x0B PHY Genesys [0x3D8B] function power data
//	0x0C PHY reserved
//	0x0D PHY reserved
//	0x0E PHY reserved
//	0x0F PHY reserved
//	0x10 USB_PARAM5(FDIO drive)		0x3D25  I2
//	0x11 DRIVER_CTRL0(FOE/FWE)		0x3D2F  I2
//	0x12 guwMaxCnt_H
//	0x13 guwMaxCnt_L
//	0x14 guwMinCnt_H
//	0x15 guwMinCnt_L	    can not set 0
//	0x16 gubthreshold		
//	0x17	
//	0x18	
//	0x19	
//	0x1A
//	0x1B
//	0x1C
//	0x1D
//	0x1E
//	0x1F

//0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F  
  01 01 00 00 46 04 00 00 0D 0C 00 00 00 00 00 00 2A 33 08 42 04 74 1E 00 00 00 00 00 00 00 00 00

[MMC_EXT_CSD]
//	0x00 Format Control x 1
//	0x01 Format Control x 2
//	0x02
//	0x03
//	0x04
//	0x05
//	0x06
//	0x07 [0x58], power good detect status
//	0x08 [0x59], LDO control #1, 
//	0x09 [0x5A], LDO control #2,
//	0x0A [0x5B], flash even delay control,
//	0x0B [0x5C], OSC control,
//	0x0C [0x5D], LED RS control
//	0x0D [0x60], watch dog timer
//	0x0E [0x61], password silo SHA-256
//	0x0F Target OSC Frequency( Unit: MHz ), Input (ex: 85MHZ = 0x55,120MHZ = 0x78)
//	0x10 used by PDT. guwBEMainFreq HIGH byte
//	0x11 used by PDT. guwBEMainFreq LOW byte
//	0x12 used by PDT. guwMaxBEMainFreq HIGH byte
//	0x13 used by PDT. guwMaxBEMainFreq LOW byte
//	0x14 used by PDT. guwMinBEMainFreq HIGH byte
//	0x15 used by PDT. guwMinBEMainFreq LOW byte
//	0x16 Delay count I0		
//	0x17 Delay count I2	
//	0x18 Enable 2 plane Cache Read	
//	0x19 Write LBA HIGH byte flash x 1	
//	0x1A Write LBA MID byte  flash x 1
//	0x1B Write LBA LOW byte  flash x 1	
//	0x1C Write LBA HIGH byte flash x 2
//	0x1D Write LBA MID byte  flash x 2
//	0x1E Write LBA LOW byte  flash x 2
//	0x1F

//0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F  
  00 00 00 00 14 33 05 00 01 18 00 05 01 02 00 00 00 00 00 00 00 00 3A 40 00 00 00 00 00 00 00 00  
//00 00 00 00 14 33 05 00 07 28 00 07 01 02 00 5F 00 00 00 00 00 00 3A 40 00 00 00 00 00 00 00 00

[MULPAGE_WRITE_CMD_SET]
//2 plane write
//80 10 11 81 85 70 10 00 FC 11 00 00

//1 plane write
80 10 10 80 85 70 10 00 FC 11 00 00
//2 plane cache write
//80 15 11 81 85 70 10 00 FC 11 00 00

[MULPAGE_READ_CMD_SET]
//1 plane read
00 30 00 E0 05 70 00 00 6E 10 00 00
 
//2 plane read
//60 30 00 E0 05 70 E0 00 7E 74 00 00

//2 plane cache read
//?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ??

[MULPAGE_CB_CMD_SET]
00 10 10 00 85 70 35 00 FC 42 00 00

[MULBLOCK_ERASE_CMD_SET]
//60 D0 00 60 00 70 00 00 2C 20 00 00
//1 plane erase
60 D0 00 00 00 70 00 00 0C 01 00 00

[SD_SCR]
// (A) SD 2.0/SD 1.x
01 25 00 00 00 00 00 00

// (B) SD 1.01
//00 25 00 00 00 00 00 00

[SD_SIZE_OF_PROTECTED_AREA]
// card density is less than 1GB(< 1GB)
00 00 00 00

// card density is larger than or equal to 1GB(>= 1GB)
//00 00 00 30	//	AG-AND
//00 00 00 50	//	Others                                                                
                                                              